一种应用于GSM接收机频率合成器的多模分频器

A Multi-Modulus Frequency Divider for Synthesizers in GSM Receiver

介绍了一个多模分频器的设计。为了提高工作速度,采用吞脉冲(pulse-swallow)结构,并且两个计数器均采用改进的检测与置数逻辑;但经过分析,发现在吞脉冲结构下,采用该改进逻辑会存在时序问题。文章提出一种解决方法。经SpectreRF模拟,在SMIC 0.18μm CMOS工艺条件下,最高工作频率可达3.7 GHz,消耗电流1.4 mA,芯片版图面积150μm×130μm。

A multiple modulus frequeney divider was proposed. Using a pulse-swallow architecture and a new detecting and reloading algorithm, the divider＇s speed was improved greatly. However, with the pulse-swallow architeeture, the proposed reloading algorithm may result in a timing problem, which was solved by introducing an extra building block. The divider was implemented in SMIC＇s 0. 18 μm CMOS process, with a maximum operating frequency of 3.7 GHz and a current consumption of 1.4 mA. The chip occupies an area of 150 μm×130μm.