0.18μm CMOS工艺栅极氧化膜可靠性的衬底和工艺依存性

Substrate and process dependence of gate oxide reliability of 0.18μm dual gate CMOS process

用斜坡电压法(Voltage Ramp,V-ramp)评价了0·18μm双栅极CMOS工艺栅极氧化膜击穿电量(Charge toBreakdown,Qbd)和击穿电压(Voltage to Breakdown,Vbd).研究结果表明,低压器件(1·8V)的栅极氧化膜(薄氧)p型衬底MOS电容和N型衬底电容的击穿电量值相差较小,而高压器件(3·3V)栅极氧化膜(厚氧)p衬底MOS电容和n衬底MOS电容的击穿电量值相差较大,击穿电压测试值也发现与击穿电量相似的现象.其原因可以归结为由于光刻工艺对多晶硅/厚氧界面的损伤.该损伤使多晶硅/厚氧界面产生大量的界面态.从而造成了薄氧与厚氧n衬底和p衬底MOS电容击穿电量差的不同.从Weibull分布来看,击穿电压Weibull分布斜率比击穿电量.击穿电压的分布非常均匀,而且所有样品的失效模式都为本征失效,没有看到“尾巴”,说明工艺非常稳定.

V-ramp method was used to evaluate gate oxide reliability of 0. 18μm dual gate CMOS process. Charge of breakdown （ Qbd ） and voltage of breakdown （Vbd） of gate oxide with n-type substrate and p-type substrate were extracted. It was found that for low voltage （thin oxide） gate oxide device the Qbd of gate oxide of n-type substrate and p-type substrate are almost the same, but for high voltage （thick oxide） gate oxide device the Qbd of n-type substrate and p-type substrate have a big difference. At the same time, Qbd of gate oxide with p-substrate is bigger than that of gate oxide with n-substrate. The difference of Qbd of thin gate oxide and thick gate oxide can be attributed to lithographic damage to the interface of poly-silicon gate and thick gate oxide. There is a big difference between the Weibull slopes of charge of breakdown of thin oxide and thick oxide. For the voltage of breakdown, Similar difference between n-substrate and p-substrate gate oxide was also observed. However, there is no big difference between the Weibull slopes of voltage of breakdown of thin oxide and thick oxide.