一种基于晶体管逻辑状态的电路简化方法

A new method of circuit reduction based on logic state of transistor

本文提出了一种存储器(Memory)逻辑参数提取的电路简化新方法。该方法通过判断在输入特定激励向量时晶体管的逻辑状态是否改变来简化电路,研究表明新方法能大幅度减少电路中晶体管的数量,同时能很好地保持电路原有的功能特性和电气特性。基于此方法测得的逻辑参数有较好的精度,并大大加快了提取速度。实验结果表明该方法是有效的。

A new method of circuit reduction for memory logic parameter is proposed. The method simplifies the circuit by judging whether logic state of transistor alters or not while inputting specialized stimulate wave. The studies show it reduces the number of the transistor greatly and holds nicely functional performance and electrical characteristic of circuit. The precision of logic parameter extracted by this new method is very good and it cuts short greatly the extraction time. The experimental results show that it is efficient.