基于组合解压缩电路的多扫描链测试方法

A Multiple-Scan-Chain Test Approach Based on Combinational Decompression Circuits

提出一种采用组合电路实现解压缩电路的压缩方法,只需少量的输入管脚,可以驱动大量的内部扫描链·该方法利用确定性测试向量中存在的大量的不确定位(X位),采用对测试向量进行切片划分和兼容赋值的思想,通过分析扫描切片之间的兼容关系来寻找所需的外部扫描输入管脚的最小个数·实验结果表明,它能有效地降低测试数据量·此外,通过应用所提出的解压缩电路,扫描链的条数不再受到自动测试仪的限制,因此能充分发挥多扫描链设计降低测试应用时间的优点·

An on-chip decompressor is an efficient method to reduce test cost in multiple scan chain designs. In this paper, a new technique is investigated to implement the decompressor by utilizing combinational circuits. The proposed architecture drives a large number of internal scan chains with far fewer external input pins, thus delivering significant reductions in test data volume. Based on the analysis of compatible relationships among scan slices, the number of external scan inputs can be minimized. The effectiveness and applicability of the proposed scheme are demonstrated by experimental results.