USB接口引擎的软核设计与FPGA兑现

FPGA Implementation and Design of USB SIE IPCore

在USB Open Core的基础上,对USB接口引擎进行RTL级的Verilog HDL语言功能设计和FPGA兑现验证。主要介绍了USB通讯协议的基本原理,根据USB接口引擎的结构框图,说明各功能模块的设计思路和方法,并在ModelSim中进行功能仿真分析,最后下载到Xilinx公司的FPGA中进行综合。

On the basis of USB Open Core,a novel USB SIE （Serial Interface Engine） logic block architecture is designed. The USB SIE is partitioned into several temporally independent functional modules,and each of which is designed with RTL （Register Transfer Level） individually. All the modules are then integrated into one design and simulated successfully. The USB SIE logic blocks are synthesized and implemented on FPGA successfully.