SoC硬件综合设计中基于Verilog语言的接口程序设计

Interface Design Based on Verilog Language in SoC Hardware Interface Synthesis

针对系统芯片SoC(System-on-Ch ip)设计中IP复用问题,提出了一种基于状态机FSM(F in iteState M ach ine)自动生成的SoC硬件接口综合设计方法,给出了基于Verilog语言的接口程序设计,通过实例仿真验证了该方法的可行性。该方法可以自动化生成接口程序,对于缩短SoC芯片设计时间,提高IP复用程度等方面提供了一种新的方法。

Aiming at the problem of IP duplicate usage in the design of SoC （ System-on-a-Chip）, a hardware interface synthesis method is presented based on the automatic generating by the finite state machine. The interface program based on the hardware description language Verilog is given. The way to formulate the interface program is given. The method is verified through the practical example. The interface program can be generated automatically by using the method. The new method may shorten the design time of SoC and solve the duplicate usage of IP.