全搜索运动估计算法的高效VLSI结构设计

An Efficient VLSI Architecture Design for Full Search Block-matching Algorithm

提出了一种具有可重构寄存器阵列的高效树型运算结构。该结构具有100%的PE利用率。同传统的全树型结构相比,在具有相近处理能力的情况下,它的输入数据带宽得到了大幅度降低。采用该设计思想实现了一个具有256个PE的电路,用于处理16×16的宏块。该电路在工作频率为55 MH z时就可以满足搜索区域是[-16,16]、帧率为30 fps和帧尺寸为720×576的视频序列的实时压缩处理要求。此时,该结构的处理能力比相近硬件规模的AB 2结构提高了31%,输入数据带宽仅为全树型的1/16。

The computing architecture is very important in the hardware architecture for motion estimation. An efficient computing architecture with a reconfiguable register array is proposed. Its PE efficiency is 100%. Compared with the full tree, the architecture has the same speed while its input width is decreased. A computing architecture with 256 PEs was implemented for the 16× 16 block. Under a clock frequency of 55 MHz, it allows the real-time processing of 720×576 at 30 fpsin a search range [-16,16]. In this situation, its speed is 31% higher than AB2＇s. Moreover, our architecture＇s input width is only 1/16 of the full tree＇s.