高速RS(31,15)编码器的IP核设计

The IP Core Design of High-Speed RS(31,15) Encoder

在现代移动通信系统中,RS码得到广泛应用,它除了有很强的纠正随机错误能力外,还非常适合于纠正突发错误。本文设计的是应用于具有瑞利衰落信道的移动通信系统中的RS(31,15)编码器。RS编码器IP核设计的难点是提高编码电路的编码运算速度。本文采用基于多项式乘法理论的GF(25)上5位标准基乘法器,并对其进行优化,提高了编码电路中乘法器模块的运算速度,从而解决了运算速度慢的问题,同时使用VerilogHDL语言和QuartusⅡ软件,设计了RS(31,15)编码器,通过仿真及硬件测试验证了设计的正确性。

Reed Solomon forward error correcting codes have been commonly applied in modern mobile communication. In addition to strong capability of correcting random occurring errors, it is also suitable for coping with bursterrors, This design of RS（31,15） Encoder is applied to Rayleigh Channel for mobile communication. The difficulty of the design is to improve the rate of encoder. The five criteria based multiplier based on the theory of polynomial in the field of GF（2^s） is adopted and optimized so as to enhance the velocity solving the problem of slow processing. RS（31,15） eneoder is implemented using Verilog HDL language and Quartus Ⅱ software and the implementation is verified through simulation and hardware testing.