CPLD在数字给定中的应用

Digital Given Unit Based on Complex Programmable Logic Device

介绍了一种基于复杂可编程逻辑器件的数字给定单元的设计方案.在原有电路的基础上,采用了ALTERA公司的MAX7000系列器件.MAX7000产品采用先进的CMOS工艺制造,基于电可擦除可编程的只读存储器(EEPROM),提供密度范围从600到10000的可用逻辑门,速度达3.5ns的管脚到管脚延迟.MAX7000器件支持在系统可编程能力(ISP),可以在现场轻松进行重配置.整个设计节省了元件数目,简化了电路设计,而且满足了现代电路日益向高集成度方向发展的要求.

This paper introduces a design scheme, which is a kind of digital given unit based on Complex Programmable Logic Device. According to the old circuit, the new system adopts MAXT000 programmable logic device family produced by Altera. Manufactured on an advanced CMOS process, based on electrically-erasable programmable read-only memory （EEPROM）, offer densities from 600 to 10 000 usable gates with pin-to-pin delays as fast as 3.5 ns. MAX7000 devices support in-system programmability （ISP） and can be easily reconfigured in the field. All these not only economize elements but also make the designing simple, and meet the requirement of development ofhigh-integration density circuit.