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An Ultra-Low-Power Embedded EEPROM for Passive RFID Tags 被引量：1

一种适用于射频电子标签的超低功耗嵌入式EEPROM(英文)
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摘要 An ultra-low-power,256-bit EEPROM is designed and implemented in a Chartered 0.35μm EEPROM process. The read state power consumption is optimized using a new sense amplifier structure and an optimized control circuit. Block programming/erasing is achieved using an improved control circuit. An on silicon program/erase/read access time measurement design is given. For a power supply voltage of 1.8V,an average power consumption of 68 and 0.6μA for the program/erase and read operations,respectively,can be achieved at 640kHz. 采用Chartered0.35μmEEPROM工艺设计并实现了一个适用于无源射频电子标签的256位超低功耗EE PROM存储器.芯片实现了块编程和擦写功能,并通过优化敏感放大器和控制逻辑的结构,实现了读存储器时间和功耗的最优化.最后给出了芯片在编程/擦写/读操作情况下的功耗测试结果.在电源电压为1.8V,数据率为640kHz时,EEPROM编程/擦写的平均功耗约为68μA,读操作平均功耗约为0.6μA.
作者 闫娜 谈熙 赵涤燹 闵昊
机构地区 复旦大学专用集成电路与系统国家重点实验室
出处 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2006年第6期994-998,共5页 半导体学报（英文版）
关键词 radio frequency identification EEPROM MEMORY charge pump sense amplifier low power 射频识别 EEPROM 存储器 电荷泵 敏感放大器 低功耗
分类号 TP391.4 [自动化与计算机技术—计算机应用技术] TP333 [自动化与计算机技术—计算机系统结构]
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参考文献8

  • 1Finkenzeller K.RFID handbook:fundamentals and applications in contactless smart cards and identification.2nd ed.New York:Wiley,1999
  • 2Glidden R,Bockorick C,Copper S,et al.Design of ultra-lowcost UHF RFID tags for supply chain applications.IEEE Comm Magazine,2004,42(8):140
  • 3Chrisanthopoulos A,Moisiadis Y,Varagis A,et al.A new flash memory sense amplifier in 0.18μm CMOS technology.The 8th IEEE International Conference on Electronics,Circuits and Systems,2001,2:941
  • 4Dickson J.On-chip high-voltage generation MNOS integrated circuits using an improved voltage multiplier technique.IEEE J Solid-State Circuits,1976,SC-111:374
  • 5Pelliconi R,Iezzi D,Baroni A,et al.Power efficient charge pump in deep submicron standard CMOS technology.IEEE J Solid-State Circuits,2003,38 (6):1068
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  • 7Xu Fei,He Xiangqing,Zhang Li.Key design techniques of a 40ns 16K bits embedded EEPROM memory.International Conference on Communications,Circuits and Systems,2004,2:27
  • 8Sharma A K.Semiconductor memories:technology,testing,and reliability.1st ed.New York:Wiley-IEEE Press,2002

同被引文献4

  • 1YANG J J, PICKETT M D, LI X M, et al. Memristive switching mechanism for metal/oxide/metal nanodevices [ J ]. Nature Nano Technology, 2008, 3:429 -433.
  • 2WEI Z, KANZAWA Y, ARITA K, et al. Highly reliable TaOx ReRAM and direct evidence of redox reaction mechanism [ J ]. Proceedings of IEEE International Electron Devices Meeting. San Francisco, CA,USA, 2008:1 -4.
  • 3LEE J, KIM B. A low-noise fast-lock phase-locked loop with adaptive bandwidth control [ J ]. JSSC, 2000, 35 ( 8): 1137 - 1145.
  • 4BANBA H, SHIGA H, UMEZAWA A, et al. A CMOS bandgap reference circuit with sub-l-V operation [ J]. IEEE J Solid-State Circuits, 1999, 34(5) : 670 -674.

引证文献1

Journal of Semiconductors
2006年 第6期

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