期刊文献+

High-Speed,Robust CMOS Dynamic Circuit Design

高速抗噪声CMOS动态电路设计(英文)
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摘要 A novel circuit with a narrow pulse driving structure is proposed for enhancing the noise immunity and improving the performance of wide fan-in dynamic circuits. Also,an analytical mode that agrees well with simulations is presented for transistor sizing. Simulation results show that an improvement of up to 12% over the conventional technique at 1GHz is obtained with this circuit,which can run 1.6 times faster than the existing technique with the same noise immunity. 提出了一种利用窄脉冲发生器驱动输出级,以提高电路抗噪声能力,同时保持动态电路的高速特性的多输入动态逻辑电路.提出了这种电路的分析模型,用于说明电路的抗噪声特性和管子的参数设置.在0.18μmCMOS工艺,1.8V的Vdd电压和55℃的环境温度下,模拟结果表明:与现有的两种技术相比,在相同的最坏延时情况下,新结构具有更好的抗噪声能力,分别提升了12%和8%;而在具有相同的抗噪声能力的情况下,新结构具有更快的速度,分别提高了1.6倍和1.4倍.
出处 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2006年第6期1006-1011,共6页 半导体学报(英文版)
关键词 domino circuit noise immunity HIGH-SPEED KEEPER narrow pulse 多米诺电路 抗噪声能力 高速 电荷保持器 窄脉冲
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参考文献7

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