基于Viterbi设计最大似然序列检测器

Design Most Likelihood Sequence Detector Based on FPGA

有记忆信号的观测值是相互关联的,传统检测方法不能达到最佳效果。本文提出一种基于维特比算法的最大似然序列检测器,Viterbi算法将ML序列检测器执行的网格路径搜索的数量减到最小,采用全并行方案,用FPGA作为硬件载体,从而获得更快的速度和更小的电路规模。

As the observation value of memory signal is mutually connected,the traditional detection method cannot achieve best.This paper proposed an algorithm to most likelihood sequence detector based on Viterbi,ML sequence detector will reduce searching quantity of the grid way to smallest.If carries out Viterbi algorithm,it may obtain a quicker speed and smaller electric circuit scale introducing parallel scheme and with FPGA as the hardware carrier.