无线通信系统维特比译码的FPGA仿真验证

FPGA Simulation Verification of Viterbi Decoder in Wireless Communication System

在设计宽带无线通信系统的基带平台中,采用一种基于FPGA仿真工具Active HDL和目前广泛用于数字信号处理、数值分析等的实用软件Matlab相结合的方法,通过实现(2,1,7)卷积编码的全并行维特比软判决译码的FPGA设计仿真和算法验证,提出一种利用Matlab进行测试向量的生成和验证,以简化仿真测试序列的手工输入,提高FPGA设计进程和保证代码质量的方法。

In this paper, the baseband platform for wideband wireless communication system,is designed using FPGA, The FPGA algorithms are simulated by Active HDL,a simulation tool for FPGA,and also Matlab.a software for digital signal processing and numeric analysing. A full parallel soft decision Viterbi Decoder of （2, 1,7） convolution code is simulated using these tools above, The method proposed in this paper,is to simplify the manual importing of simulation testing sequence,so as to promots the development of FPGA design and prove the quality of FPGA codes,