摘要
描述了用于SDH光纤通信STM-16速率级的2.488Gbit/s时钟和数据恢复电路.该电路采用基于注入式锁相环和D触发器的电路结构,在标准的0.35μmCMOS工艺上实现流片.经过测试,当输入长度为231-1的伪随机序列,数据速率为2.488Gbit/s时,在误码率为10-12的条件下,电路的灵敏度小于20mV.恢复得到的时钟具有2.8ps的均方根相位抖动,在100kHz频偏处的相位噪声为-110dBc/Hz,并具有大于40MHz的捕获范围.5V电源供电时,电路消耗680mW功率.芯片面积为1.49mm×1mm.
The design of a 2. 488 Gbit/s clock and data recovery (CDR) If for synchronous digital hierarchy (SDH) STM-16 receiver is described. Based on the injected phase-locked loop (IPLL) and D-flip flop architectures, the CDR IC was implemented in a standard 0. 35 μan complementary metal-oxide-semiconductor (CMOS) technology. With 2^31 -1 pseudorandom bit sequences (PRBS) input, the sensitivity of data recovery circuit is less than 20 mV with 10^-12 bit error rate (BER). The recovered clock shows a root mean square (rms) jitter of 2. 8 ps and a phase noise of - 110 dBc/Hz at 100 kHz offset. The capture range of the circuit is larger than 40 MHz. With a 5 V supply, the circuit consumes 680 mW and the chip area is 1.49 mm × 1 mm.
关键词
时钟恢复
数据恢复
锁相环
预处理器
clock recovery
data recovery
phase-locked loop (PLL)
preprocessor