摘要
文章介绍了一种基于查找表的二元单调函数的幅值增量比较算法及其FPGA硬件电路设计实现,通过改变查找表的存储数据和函数值的输出方式来实现函数值的输出。与传统的实现算法相比较,该算法将节约95%以上的ROM。
This paper has presented a solution for binary monotonically function based on LUT and the way of implementing it by FPGA. The presented algorithm based on magnitude incremental comparison outputs the value by changing.the stored data of the look-up table and the way of outpufing the value. Compared to the conventional method, this algorithm has saved more than 95% ROM.
出处
《微电子学与计算机》
CSCD
北大核心
2006年第7期140-142,共3页
Microelectronics & Computer