数字电路的VHDL语言设计方法

Design Method of Digital Circuit Based on VHDL Language

分析了传统硬件电路设计的“自下而上”的方式和步骤,针对设计中存在的调试与试验相对滞后的问题,提出了采用“自上而下”的VHDL电路设计方法,按照硬件设计的三个层面,对行为级描述、寄存器传输级描述和逻辑综合进行了说明并给出了电路设计流程,通过SCI设计实例对该设计方法做了进一步的诠释和具体分析,为数字电路的VHDL语言设计提供了可借鉴的思路和方法.

The design method and process of Bottom to Up in the traditional hardware circuit were analyzed. The VHDL design was put forward in order to resolve the issue. According to hardware design three layers principle, the action level description, register transmission level （RTL） and the logical integration were described. The design flowchart was presented. The design method based on the SCI example was analyzed for the purpose of providing the available method and means to the digital circuit VHDL language design.