内部高速计数器实验电路改进设计

Improving Design of Experimental Circuit of Internal High Speed Counter

介绍了基于PLC(可编程逻辑控制器)编程的内部高速计数器验证电路的实验过程。该计数器采用PLC作为核心控制器,是高等学校自动化与控制专业实验教学中为进一步提高学生的实践能力和创新能力而引进的一个实验电路。针对自动化与控制专业的特点,从电路设计及梯形图设计出发,设计了系统的硬件和软件,并在联机实验过程中发现了问题,找出失败机理。通过分析改造实验电路,顺利完成了内部高速计数器外部输入信号的实验。实验结果表明,系统是稳定的,达到了预期的目标,解决了实验过程中存在的问题。

We describe the validating process of experimental circuit of Internal High Speed Counter. Starting with the Electronic circuit design and echelon figure design, we recognize the problems in practice and the mechanizm of their failure. Finally, we made experiments of inputting signals from the external to internal High Speed Counter after analyzing and improving the circuit. The problems in experiment are finally solved.