一种新的高效数字下变频方法及其FPGA实现

A new method of making high-efficiency digital down-conversion and the implementation through FPGA

数字接收机是新一代雷达侦察系统的主要组成部分。本文对数字接收机结构进行了研究,提出了一种高效数字下变频方法。该方法的运算量是传统DDC方法的1/M,并且可以简单地实现和多相滤波一样的运算效果。仿真及实验证明,该结构是实现数字下变频的高效结构,有利于硬件资源的节省。

The digital receiver is an important part of the new-generation radar detection system. Based on the discussion of the structure of digital receiver, an effective method of making digital down-conversion （ DDC ） is presented. With remarkably lowered workload of making FIR filtering, which is only 1/M of that of the traditional DDC method, this method achieves the same results as the polyphase filtering structure does through easier implementation. Simulations proves that this method is very capable of making DDC and can save the resource of hardware.