复杂可编程逻辑器件的设计技术

The Design and Technology of the Complex Programmable Logic Device

介绍了复杂可编程逻辑器件(CPLD)的设计技术,重点叙述了复杂可编程逻辑器件架构的设计,关键单元设计技术。采用0.35μm内嵌Flash工艺进行模拟仿真和全定制版图设计,该复杂可编程逻辑器件(CPLD)具有72个宏单元,系统频率可达85MHz,管脚延时可达7ns。

The paper described the design method and technology of the Complex Programmable logic Device （CPLD）. The architecture and key circuit design of the CPLD were researched. The analog simulation and full custom layout design with 0.35μm imbedded flash process were used. The CPLD had 72 macro -cells, its system frequency was 85MHz and its pin -to -pin delay was 7ns.