摘要
介绍了UART_16C554可复用IP核的设计,通过对器件进行结构划分,RTL级代码的设计,功能仿真,FPGA原型的验证,最终形成了一个与硬件16C554完全兼容的可复用IP核。
In this paper, a reuse IP core design of UART_16C554 is described. With the architecture design, RTL- level design, functional simulation, and FPGA prototype verification, the UART_16C554 is a reuse IP core that fully compatible with de -facto 16C554.
出处
《微处理机》
2006年第3期19-21,共3页
Microprocessors
关键词
设计复用
异步通信
接收
发送
Reuse
Asynchronous communication
Receiver
Transmitter
