摘要
提出了一种高性能低电压无死区鉴频鉴相器(PFD)电路,并通过时钟分析优化其设计参数。阐述了恢复时间对PFD电路最大工作频率的影响以及降低PFD恢复时间的设计方法,仿真结果同理论极为相符。
A high- performance low voltage dead- zone free Phase- Frequency Detector（PFD） is presented and it＇s parameters are optimized through an extensive timing analysis. It explains the impact of reset time issues on the maximum operating frequency of the PFD. Excellent agreement among theory and simulations to minimize the reset time in the PFD is observed.
出处
《微处理机》
2006年第3期78-80,84,共4页
Microprocessors
