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超深亚微米工艺时代集成电路设计领域所面临的技术挑战 被引量:3

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摘要 集成电路工艺加工能力的不断提高给设计工作带来了多方面需要解决的问题。本文主要探讨目前在集成电路设计领域各个方面的设计技术挑战和研究热点问题。
作者 蒋安平
出处 《中国集成电路》 2006年第7期29-33,64,共6页 China lntegrated Circuit
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同被引文献19

  • 1微电子学、集成电路[J].中国无线电电子学文摘,2007(2). 被引量:1
  • 2陈秀华,王莉红,项金钟,吴兴惠,周桢来.超大规模集成电路铜布线扩散阻挡层TaN薄膜的制备研究[J].功能材料,2007,38(5):750-752. 被引量:8
  • 3周继承,陈海波,李幼真.纳米Ta-Al-N薄膜的制备及其扩散阻挡特性的研究[J].真空科学与技术学报,2007,27(4):327-331. 被引量:2
  • 4Spencer K M, Kewal K S. A test partitioning technique for scheduling tests for thermally constrained 3D integrated circuits[C] //Proc of the 27th International Conference on VLSI Design and the 13th International Conference on Embedded Systems. [S. l.] :IEEE Press, 2014:20-25.
  • 5Yao Chunhua, Saluja K K , Ramanathan P. Partition based SoC test scheduling with thermal and power constraints under deep submicron technologies[C] //Proc of Asian Test Symposium. [S. l.] :IEEE Press, 2009:281-286.
  • 6Zhao Dan, Upadhyaya S. Dynamically partitioned test scheduling with adaptive TAM configuration for power-constrained SoC testing[J] . IEEE Trans on CAD of Integrated Circaits and Systems, 2005, 24(6):956-965.
  • 7Liu Chunsheng, Veeraraghavant K, Iyengar V. Thermal-aware test scheduling and hot spot temperature minimization for core-based systems[C] //Proc of IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. 2005:552-562.
  • 8He Zhiyuan, Peng Zebo, Eles P. A heuristic for thermal-safe SoC test scheduling[C] //Proc of IEEE International Test Conference. 2007:1-10.
  • 9Bild D R, Misra S, Chantemy T, et al. Temperature-aware test scheduling for multiprocessor systems-on-chip[C] //Proc of IEEE/ACM International Conference on Computer-Aided Design. [S. l.] :IEEE Press, 2008:59-66.
  • 10Skadron K, Stan M, Huang Wei, et al. Temperature-aware microarchitecture[C] //Proc of the 30th Annual International Symposium on Computer Architecture. [S. l.] :IEEE Press, 2003:2-13.

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