利用ADC输出码密度测量时钟抖动的仿真研究

Simulation research on jitter measurement using CDF of ADC output code

在已有的利用ADC采样研究时钟抖动基本模型的基础上,提出了利用ADC的输出码密度测量时钟抖动的修正模型.考虑了量化噪声的影响,利用信噪比关系,根据修正模型导出了最佳性能公式.最后通过MATLAB对这个修正模型进行了仿真验证,并指出可以利用修正模型对实际测量结果进行修正.

On the basis of the old model of ADC input clock jitter and signal, a formula functioned with ADC input clock jitter and ADC output code cumulative probability distribution function was deduced. Using the SNR expression, a formula about the best performance that the revised model could reach was given. By using the tool of MATLAB, this model was simulated and the deduced formula was verified. The result shows that the revised model can be used to amend the jitter data of actual measurement,