维特比译码器实现中的关键技术

Key techniques in implementation of the Viterbi algorithm

本文针对维特比译码算法中的两个关键问题,即路径寄存器溢出与幸存路径存储问题,分别提出了可行的解决方案,并应用该方案在XilinxSpartanIIFPGA上实现了速率为64Kb/s的软判决译码器。

This paper aims at solving two problems in the implementation of Viterbi algorithm, which are path metrics overflow and survivor sequence storage. Based on these, a 64Kb/s soft - decision Viterbi decoder was implemented on Xilinx Spartan Ⅱ FPGA.