超长指令字DSP处理器的共享寄存器堆设计

The Design of Shared Register File for VLIW DSP Processors

共享数据寄存器堆设计是超长指令字DSP处理器实现的难点。它的访问延时成为处理器的关键延时之一。在一高性能超长指令字DSP处理器的设计中,通过对传统单周期读写寄存器堆的设计方案进行深入的分析和研究,优化关键路径,设计出双周期读写结构的寄存器堆。通过电路实现比较后证实,双周期方案在减少27%访问时间的同时减少23%的面积。

The design of shared data register file is the hardest for implementation of VLIW （ Very Long Instruction Word） DSP （Digital Signal Processing） Processors. Its access time could be one of the critical delays. In the design of a high performance VLIW DSP Processor, a new two-stage-access design is promoted, based on the detail analysis and study of the traditional one-stage-access design, in order to optimize the critical delay. After comparing of the performance of the implementations of two types of design：, it is clear that the using two-stage-access structure reduces the access time by 27%, while saving the area by 23%.