VLSI边界扫描测试故障诊断及其策略研究

Research on the Boundary-Scan Test Bus Fault Diagnosis and Its Strategy for VLSI

介绍了支持JTAG标准的IC芯片结构和故障测试的4-wire串行总线,以及运用边界扫描故障诊断的原理。实验中分析了IC故障类型、一般故障诊断流程和进行扫描链本身完整性测试的方案,并提出了一种外加测试码向量生成的算法。该故障诊断策略通过两块xc9572pc84芯片互连PCB板的实现方法进行验证,体现了该策略对于芯片故障定位准确、测试效率高、控制逻辑简便易行的优越性。

The IC chip structure that supports JTAG standard, 4-wire serial bus and fault diagnosis principles of the boundary scan test bus were introduced. In the experiments, the fault type of IC test bus, the fault diagnosis flow and the test principles were analyzed, and a fault diagnosis strategy of test bus was proposed. This diagnosis strategy was realized on the PCB which was interconnected by two pieces chips, xc9572 and pc84. It manifested that this method is validity to localize accurately the chip fault, test highly effective, control logic simply and conveniently, and realize easily.