嵌入式双端口SRAM可编程内建自测试结构的设计

Design of Programmable Memory BIST for Embedded Dual Ports SRAM

分析了嵌入式双端口SRAM的故障模型,并在此基础上提出了一种新型的针对嵌入式双端口SRAM的BIST结构；它能够有效地测试双端口SRAM,通过使用新型的指令格式能够减少指令数据量和测试时间。

New design of programmable memory BIST for embedded dual ports SRAM is presented based on analyzing faults model. It uses a new instruction format, so it can test dual ports SRAM efficiently. Further more, the volume of the instruction and the time for faults test can also be reduced.