基于CPLD及C语言的等精度频率计设计

The Design of Frequency Meter for Equal Observations Based on CPLD and C Language

主要介绍了等精度频率测量原理,该原理具有在整个测试频段内保持高精度频率测量的优点;同时在该原理基础上,采用了VerilogHDL语言设计了高速的等精度测频模块,并且利用EDA开发平台QUARTUSⅡ3.0对CPLD芯片进行写入,实现了计数等主要逻辑功能;还使用C语言设计了该等精度频率计的主控程序以提高测量精度。本设计实现了对频率变化范围较大的信号进行频率测量,能够满足高速度、高精度的测频要求。

This paper mainly introduces the principle of equal observations for frequency, which has the merit of keeping high degree of accuracy for frequency measurement in entire test wave band; meanwhile, on base of this principle, adopts Verilog HDL to design high speed integrated circuit for equal observations of frequency, and uses EDA development tool QUARTUS 11 3.0 to program CPLD, realizes main logic function such as counter; and uses C language to design the main control program of the frequency meter for equal observations to make the meter more accurate. The design has realized broad band measurement and can meet the request of high speed and high degree of accuracy.