锁相环路计算机辅助分析的一种方法

A Computer Aid Analysis Method for Phase-locked Loops(PLL)

提出了一种面向系统数学模型的模块连接式锁相环路计算机辅助分析方法。利用该方法，可对任意类型锁相环路的工作过程、时域特性、频域特性、捕捉过程及输入叠加噪声对锁相环路的影响等多方面进行计算机辅助分析，其特点是：１）原理简明，编程简单；２）不受锁相环路阶数、输入信号形式及鉴相器类型的限制，可分析各种线性及非线性的锁相环路，适应能力强；３）可分析随机叠加输入噪声对锁相环路性能的影响；４）锁相环路各点工作状态均可用图形直观显示，辅助分析能力强。

A computer aid analysis method for PLL of block-linking type facing systematic mathematical models is proposed. Using the method the computer aid analysis on time-domain property,frequences-domain property, the catching process and the input-superimposed noise influencing the PLL and many other aspects of any type of PLL can be conducted. Their major characteristics are:1) the simplicity and clarity of their principles and the easiness in programming;2) not restricted by the order of PLL, the style of the input signals and the types of phase detector; applicable in analysis of various linear and non-linear PLL; with high adaptability; 3) applicable in the analysis of the affects of randomly input superimposed noise to the performances of PLL;4) The working state of all points in the PLL can be visibly displayed, with high ability in aid analyses.