一种基于AHB总线的高速存储访问机制的设计与实现

Design and Implementation of an AHB-based High-Speed Memory Access Layer

系统芯片中的高速IO设备一般需要直接存储访问(DMA)功能的支持,以减轻处理器的负担,提高系统性能和IO性能.考察了片上系统总线和DMA访问机制的特性,设计实现了一种基于AHB总线的高速存储访问机制,采用专门的接口支持以太网络接口与系统主存之间的数据传输.在总线接口的设计中提出了总线访问的优化策略,并给出了一种确定FIFO设计参数的分析方法.实验结果表明,该访问机制提高了数据传输速率,有效地支持系统芯片的网络应用.

For high-speed I/O devices in System-on-a-chip （SoC）, DMA support will relieve the processor from data transfer, and improve the performance of the overall system. This paper investigates the features of on-chip system bus and DMA mechanism, and design an AHB-based High-speed Memory Access Layer that supports data transfer between ehternet network interfaces and system memory. In the implementation of HMAL, the bus interface design is optimized, and an analytical method is proposed for determining the FIFO design parameter. Experimental results show that HMAL promotes the data transfer rate effectually and support network application-specified SoCs.