基于FPGA先进加密算法(AES)的高速实现

FPGA Optimization Implementation for AES Algorithm

在介绍有限域的概念及Rijndael算法结构,详细分析算法中基于GF(28)加法、乘法运算过程的基础上,详细阐述了使用FPGA高速实现运算关键部分的设计思路。针对FPGA设计中对速度与面积两项指标的不同要求,分别给出了两种方案,最后,给出本算法在FPGA实现方式下的性能指标。通过与国内外部分相关测试数据比较,该优化算法的性能比(MBps/Slice)明显优于其它设计。

This paper introduces the concept of finite-field as well as Rijndael Algorithm structure, and also describes the design thinking of the key part in applying FPGA high speed operation in details based on the detailed analysis of the operation process of addition and multiplication on the GF（28） grounds in algorithm. With an aim at the different requirements of two indexes of speed and area in FPGA design, two kinds of schemes are given. Finally, the performance indexes in this algorithm are given based on FPGA implementation. Via the comparison of the part correlated testing data both home and abroad, the performance ratios（MBps/Slice） of the optimal algorithm are obviously superior to other designs.