单芯片可重构数字接收机的研究

Study of the Reconfigurable Digital Receiver on a Chip

本文从系统的小型化和可重构性出发,利用可编程系统芯片(SOPC)技术,对单芯片可重构数字接收机的实现进行了研究,给出了具体的实现方案。在此基础上,利用系统工具DSPBuilder给出了QPSK解调功能模块的FPGA仿真与硬件验证。

From the Miniaturized and reconfigurable system point of view, the realization of reconfigurable digital receiver on a chip is studied by use of SOPC technology, and the special project of the realization is given in this paper. On this basis, the FPGA emulation and hardware validation of the function block of QPSK demodulation is given by the system tool of DSP Builder.