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HDTV中面积优化的RS解码器VLSI实现 被引量：2

An Area-efficient VLSI Design of Reed-Solomon Decoder for HDTV
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摘要 提出了一种面积优化的Reed-Solomon(RS)解码器实现方法,其运用折叠结构来实现解码过程矢量运算的求解电路。该方法提高了解码器主要运算部件的复用率,缩减了其电路规模。基于TSMC0.25标准单元库的实现结果显示该文设计的解码器电路规模为约27000门,与同类设计相比规模最大可缩减39%,该设计已集成在一款符合DVB-C标准的HDTV信道解调芯片中并已通过实场测试。 This paper presents a new area-efficient VLSI implementation method for Reed-Solomon.（RS） decoder. By using the folding architecture to implement the equation solving circuits, this method can improve the reuse rate of main computation unit, simplify the hardware structure and reduce the chip area. Based on the TSMC 0.25 standard cell library, the proposed RS decoder consists of about 27 000 gates, which is about 39% smaller than the same kind of conventional ones. It has been integrated in a channel demodulation chip for HDTV and has been tested successfully in practice.
作者 郭艳飞 李占才 王沁
机构地区 北京科技大学信息工程学院
出处 《计算机工程》 CAS CSCD 北大核心 2006年第16期11-13,28,共4页 Computer Engineering
关键词 RS解码器 集成电路 数字电视 Reed-solomon decoder VLSI HDTV
分类号 TN919.32 [电子电信—通信与信息系统] TN47 [电子电信—微电子学与固体电子学]
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参考文献6

  • 1Lin S, Costello Jr D J. Error Control Coding: Fundamentals and Applications[M]. Englewood Cliffs, NJ: Prentice-Hall, 1983.
  • 2Shao H M, Reed I S. On the VLSI Design of a Pipeline Reed-Solomon Decoder Using Systolic Arrays[J]. IEEE Trans. on Computers, 1988,37(10): 1273-1280.
  • 3Hsu J M, Wang C L. An Area-efficient Pipelined VLSI Architecture for Decoding of Reed-solomon Codes Based on a Time-domain Algorithm[J]. IEEE Trans. on Circuits and Systems for Video Technology, 1997, 7(6): 864-871.
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同被引文献15

  • 1王沁,李占才,齐悦.基于两层流水线结构的FIR滤波器设计[J].电子学报,2005,33(2):367-369. 被引量：7
  • 2王沁,龙萍,张晓彤,李占才.基于DOCSIS规范的测距机制分析与嵌入式实现[J].通信学报,2006,27(9):96-101. 被引量：6
  • 3Cable Television Laboratories.Data-Over-Cable Service Interface Specifications Radio Frequency Interface Specification SPRFIv1.1 G01-050907[S].CableLabs,2005.
  • 4S Lin,D J Costello Jr.Error Control Coding:Fundamentals and Applications[M].Prentice-Hall,Englewood Cliffs,NJ,1983.
  • 5Guo Yan Fei,Li Zhan Cai,Wang Qin.An area-efficient VLSI architecture for Reed-Solomon decoder[A].In Proc.IEEE ISCIT'2005[C].Beijing,China,2005.1154-1158.
  • 6Lin Shu,Costello D J Jr.Error Control Coding: Fundamentals and Applications[M].2nd Edition.[S.l.]: Prentice-Hall,Inc.,2004.
  • 7Zhang Tong,Parhi K K.On the High-speed VLSI Implementation of Errors-and-erasures Correcting Reed-solomon Decoders[C]// Proc.of ACM GLVLSI’02.[S.l.]: ACM Press,2002.
  • 8Hsu H Y,Wu A Y.VLSI Design of a Reconfigurable Multi-mode Reed-Solomon Codec for High-speed Communication Systems[C]//Proc.of IEEE Asia-pacific Conference on ASIC.[S.l.]: IEEE Press,2002.
  • 9Shieh M D,Lu Y K,Chung S M,et al.Design and Implementation of Efficient Reed-solomon Decoders for Multi-mode Applica- tions[C]//Proc.of ISCAS’06.[S.l.]: IEEE Press,2006.
  • 10Chang H C,Lin C C,Chang F K,et al.A Universal VLSI Architecture for Reed-solomon Error-and-erasure Decoders[J].IEEE Trans.on VLSI System,2009,56(9): 1960-1967.

引证文献2

计算机工程
2006年 第16期

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