期刊文献+

千兆以太网卡芯片A/D转换电路的设计与实现

Design and Implementation of an A/D Converter for Gigabit Ethernet
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摘要 介绍了一种用于千兆以太网卡芯片的8位125 MS/s CMOS流水线A/D转换电路的设计,包括体系结构设计、电路设计与仿真、版图设计。该A/D转换电路经过TSMC 0.13μm 1P8MCMOS工艺验证,工作电压为1.5 V/2.7 V。芯片测试结果表明,设计的A/D转换电路能够满足千兆以太网卡芯片的性能要求。 An 8-bit, 125 mega-sample/s CMOS A/D converter was designed for gigabit Ethernet chip. The system architecture, circuit design and simulation, and chip layout design are described. Verified with TSMC's 0.13 /μm 1PSM process, the A/D converter circuit can operate at 1.5 V/2.7 V supply voltage. Test results show that the circuit can meet the performance requirement of the gigabit Ethernet IC.
出处 《微电子学》 CAS CSCD 北大核心 2006年第4期403-406,共4页 Microelectronics
基金 华中科技大学博士后基金资助项目
关键词 A/D转换电路 流水线结构 千兆以太网 A/D converter Pipeline structure Gigabit Ethernet
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参考文献4

  • 1Carrier sense multiple access with collision detection (CSMA/CD) access method and physical layer specifications[S].IEEE 802.3.2002.
  • 2Hatamian M,Agazzi O E,Creigh J,et al.Design considerations for gigabit Ethernet 1000 BASE-T twisted pair transceivers[A].IEEE Custom Integrated Circuit Conf[C].Santa Clara,CA,USA.1998.335-342.
  • 3Baker R J,Li H W,Boyce D E.CMOS circuit design,layout,and simulation[M].United States of America,Wiley-IEEE Press,1998.
  • 4Sumanen L.Pipeline analog-to-digital converters for wideband wireless communications[D].Ph D Thesis,Helsinki University of Technology,Department of Electrical and Communication Engineering,Finland,ISSN 951-22-6223-1,2002.108-109

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