一种低功耗SoC设计中的时钟隔离技术

A Clock Isolation Technique for Low Power SoC Design

在一些复杂的SoC中,往往要使用嵌入式存储器,而双边访问的嵌入式存储器(DARAM)常用于许多低功耗的场合。这样,用时钟的双边沿来控制存储器的读写数据是不可避免的。这种时钟用作数据(clock as data)的情况通常会在SoC设计的逻辑物理综合阶段产生很多时序收敛的棘手问题,时钟隔离电路恰好能解决这个问题。实践证明,这种改进的时钟电路结构大大减少了设计的时序收敛时间和设计流程的复杂度。

In some complex SoC designs, embedded memories, especially dual access RAMs （DARAM） for low power applications, are usually used. Therefore, it is unavoidable to use clock＇s rise and fall edges to switch between different read/write data. However, this ＂clock as data＂ situation will cause serious problems in timing closure, particularly during logic and physical synthesis. To solve these problems, a clock isolation circuit was developed. The clock isolation method has been verified to reduce the timing closure iterations and the complexity of design flow.