FPGA逻辑测试中的器件建模方法

Method of Component Modeling in FPGA Logical Test

在SoC设计中,用户可运用Verilog HDL语言对所需的电路进行描述,从而获得所需要的电路功能。在设计写入FPGA芯片之前,通常运用EDA工具对其逻辑功能进行充分模拟和测试。在测试时要模拟FPGA的支持器件的功能,此时就需要对这些器件进行建模,因而外围器件建模的好坏直接影响FPGA逻辑设计质量。针对FPGA逻辑测试提出了一种器件建模方法以及器件建模的一些规范,并结合实际项目说明了器件建模的基本过程。

Users can describe the function of target circuit. Before writing the logic design of FPGA to the chip, we usually use some EDA tools to simulate and test logical functions of the design. As the FPGA＇s supporting function to the components is to be simulated in the process of the test,we need to build a model on these components. This article firstly presents a method on how to model components and some specifications on the modeling; then, the essential process of component modeling is introduced in practice.