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利用TCAD方法优化设计金属栅CMOS工艺及电路

Optimization of design with TCAD approach for metal-gate CMOS technology and circuit
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摘要 为了降低集成电路制造工艺的成本,用计算机辅助工艺设计(TCAD)的方法开发了金属铝栅CMOS工艺.首先利用3μm金属铝栅工艺对模拟软件TSUPREM-4和器件模拟软件MED ICI进行了校准,再对金属铝栅1.5μm短沟道CMOS工艺进行器件结构、工艺和电气性能等参数的模拟,以最简约工艺在现有工艺线上成功流水了1.5μm铝栅CMOS.实际测试阈值电压为±0.6V,击穿达到11V,各项指标参数的模拟与实际测试误差在5%以内,并将工艺开发和电路设计结合起来,用电路的性能验证了工艺.利用TCAD方法已成为集成电路和分立器件设计和制造的重要方法. In order to reduce the cost of integrated circuit fabrication, the metal-gate complement-metal oxide semiconductor (CMOS) technology was developed with technology computer assistant design (TCAD) approach. After the TCAD software TSUPREM-4 and MEDICI were calibrated by 3μm metal-gate CMOS technology, the satisfactory parameters such as the structure, technology and electric performance for 1.5μm metal-gate CMOS were obtained. The simple and effective technology has succeeded in taping out on current production line. The threshold of device is ± 0. 6 V and breakdown reaches 11 V. The simulation value of each parameter is in good agreement with respective experimental result (the error is less than 5 % each). Further more, the technology has been validated through linking the technology with the circuit performances. The TCAD approach has become one of the most important methods in design and manufacture of silicon integrated circuits and discrete devices.
出处 《东南大学学报(自然科学版)》 EI CAS CSCD 北大核心 2006年第4期512-516,共5页 Journal of Southeast University:Natural Science Edition
关键词 计算机辅助工艺设计 工艺模拟 金属栅CMOS工艺 TCAD technology simulation metal-gate CMOS technology
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参考文献10

  • 1Havemann R H,Eklund R H.Process integration issues for submicron BiCMOS technology[J].Solid-State-Technology,1992,35(6):71-76.
  • 2Combs S R.Scalable retrograde p-well CMOS technology[C]//IEDM Tech Dig.Washington DC,1981:346-349.
  • 3Yeo Kiat-Seng,Samir S Rofail,Goh Wang-Ling.低压低功耗CMOS/BiCMOS超大规模集成电路[M].周元兴,张志龙等译.北京:电子工业出版社,2003:2627.
  • 4Hobler G,Selberherr S.Two-dimensional modeling of ion implantation induced point defects[J].IEEE Trans Computer-Aided Design,1988,7(2):174-180.
  • 5Hu G J,Ting C Y,Taur Y,et al.Design and fabrication of p-channel FET for 1 μm CMOS technology[C]//IEDM Tech Dig.San Francisco,1982:710-713.
  • 6Wolf S.Silicon processing for the VLSI Era:volume 3:the submicon MOSFET[M].California:Lattice Press,1995:232-240.
  • 7Chen J Y.CMOS-the emerging VLSI technology[J].IEEE Circuits and Devices Magazine,1986,2(22):16-31.
  • 8Ogura S,Tsang P,Walker W,et al.Design and characteristics of the lightly-doped drain-source (LDD) insulated gate FET[J].IEEE Trans Electron Devices,1980,27(8):1359-1367.
  • 9Shibata T,Hieda K,Sato M,et al.Optimally designed process for submicrometer MOSFETs[J].IEEE Trans Electron Devices,1982,29(4):531-535.
  • 10Rung R D,Dell C J,Walker L G.A retrograde p-well for higher density CMOS[J].IEEE Trans Electron Devices,1981,28(10):1115-1119.

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