组合电路测试生成研究及实验

TEST PATTERN GENERATION FOR COMBINATIONAL CIRCUITS

本文以门级组合电路为对象，以主路径敏化算法为基础，研究提高测试生成效率的策略．实验结果表明，按本文提出的策略所研制的测试生成系统，不仅效率较好，且得到的测试集也较小．

This paper introduces some methods of test generation for combinational gate-level circuits. Fault counter is employed to direct the test pattern generation. Critical path trace is used to compact the test pattern set. Based on above methods, a system CPS(Cmpactive Pattern Set) is developed on SUN3/260, and the experimental results are gained.