封装中的界面热应力分析

Interfacial Thermal Stress Analysis in Packaging

随着电子封装集成度的不断提高,集成电路的功率容量和发热量也越来越高,封装体内就产生了越来越多的温度分布以及热应力问题。文章建立了基板-粘结层-硅芯片热应力分析有限元模型,利用有限元法分析了芯片/基板的热应力分布,封装体的几何结构参数对应力的影响。

With the increasing of packaging integration the power and the quantity of heat of integrate circuit will increase, it will bring more and more temperature distributions and problems about thermal stresses in package. In this paper a finite element thermal stress model of substrate-adhesive-chip is established, thermal stress distribution of substrate-chip interfaces and the affects of geometrical structure on thermal stresses are analyzed by finite element method especially discuss interfacial thermal stresses distributions on chipadhesive interface and adhesive-substrate interface.