期刊文献+

1200V MR D-RESURF LDMOS与BCD兼容工艺研究 被引量:10

Design of a 1200V MR D-RESURF LDMOS and BCD Technology
下载PDF
导出
摘要 提出具有p埋层的1200V多区双RESURF(MRD-RESURF)LDMOS,在单RESURF(S-RESURF)结构的n漂移区表面引入多个p掺杂区,并在源区下引入p埋层,二者的附加场调制器件原来的场,以改善其场分布;同时由于电荷补偿,提高了漂移区n型杂质的浓度,降低了导通电阻.开发1200V高压BCD(BJT,CMOS,DMOS)兼容工艺,在标准CMOS工艺的基础上增加pn结对通隔离,用于形成DMOS器件D-RESURF的p-top注入两步工序,实现了BJT,CMOS与高压DMOS器件的单片集成.应用此工艺研制出一种BCD单片集成的功率半桥驱动电路,其中LDMOS,nMOS,pMOS,npn的耐压分别为1210,43·8,-27和76V.结果表明,此兼容工艺适用于高压领域的电路设计中. A 1200V multi-region double RESURF LDMOS with a p-type buried layer,which has multiple p regions in the n- drift layer of a single RESURF structure is proposed for improving the surface electric field,increasing the concentration of the n-drift layer,and reducing the on-resistance of LDMOS. A 1200V BCD technology based on standard CMOS technology is realized by adding pn isolation and p-top implantation. Using this technology we develop a power half bridge driver. The breakdown voltages of the LDMOS,nMOS, and pMOS are 1210,43.8, and - 27V,respectively, the BVceo of the npn is 76V in the driver. The 1200V BCD technology thus can be used in the design of HVIC.
出处 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2006年第8期1447-1452,共6页 半导体学报(英文版)
基金 国家自然科学基金(批准号:60436030) 国家"十五"军事电子预研(批准号:41308020210)资助项目~~
关键词 多区 LDMOS RESURF BCD工艺 MR LDMOS RESURF BCD technology
  • 相关文献

参考文献11

  • 1Baiocchi A.New developments in mixed bipolar/CMOS/DMOS technology for intelligent power applications.IEEE Colloquium on Integrated Power Devices,1991,2:1
  • 2Moscatelli A,Merlini A,Croce G,et al.LDMOS implementation in a 0.35μm BCD technology (BCD6).Proc of ISPSD,2000:323
  • 3Van der Pol J A,Ludikhuize A W,Huizing H G A,et al.A-BCD:An economic 100V RESURF silicon-on-insulator BCD technology for consumer and automotive applications.Proc of ISPSD,2000:327
  • 4Gagnard X,Bonnaud O.Building-in reliability,application to bipolar/CMOS/DMOS technology.Proc of IPFA,2002:147
  • 5Labate L,Moscatelli A,Stella R.Robust and performing RF LDMOS device integrated in a VLSI BCD silicon technology.Radio Frequency Integrated Circuits (RFIC) Symposium,2003:159
  • 6李泽宏,张波,李肇基,方健,杨舰.DMOS阈值电压二维模型[J].Journal of Semiconductors,2004,25(6):715-719. 被引量:4
  • 7郭宇锋,李肇基,张波,方健.阶梯分布埋氧层固定电荷SOI高压器件新结构和耐压模型[J].Journal of Semiconductors,2004,25(12):1695-1700. 被引量:14
  • 8Fang Jian,Yi Kun,Li Zhaoji,et al.On-state breakdown model for high voltage RESUEF LDMOS.Chinese Journal of Semiconductors,2005,26(3):437
  • 9Murari B,Contiero C,Gariboldi R,et al.Smart power technologies evolution.Industry Applications Conference,2000,1:8
  • 10Contiero C,Murari B,Vigna B.Progress in power ICs and MEMS,"analog" technologies to interface the real world.Proc of ISPSD,2004:3

二级参考文献24

  • 1[1]Antoniadis D A.Calculation of threshold voltage in nonuniformly doped MOSFETs.IEEE Trans Electron Devices,1984,31(3):303
  • 2[2]Maneesha,Haldar S,Khanna M K,et al.Analytical theory of two-dimensional charge sheet model for short channel MOSFETs under non linear charge control.Solid-State Electron,1995,38:197
  • 3[3]Chung S S,Li T C.An analytical threshold-voltage model of trench-isolated MOS devices with nonuniformly doped substrates.IEEE Trans Electron Devices,1992,39(3):614
  • 4[4]Choi C H,Chidambaram P R,Khamankar R,et al.Dopant profile and gate geometric effects on polysilicon gate depletion in scaled MOS.IEEE Trans Electron Devices,2002,49(7):1227
  • 5[5]Ortiz-Conde A.Rodriguez J,Garca Sánchez F J,et al.An improved definition for modeling the threshold voltage of MOSFETs.Solid-State Electron,1998,42(9):1743
  • 6[6]Lahiri S K,Dasgupta A,Manna I,et al.A quasi-3D analytical threshold voltage model of small geometry MOSFET.Solid-State Electron,1992,35(12):1721
  • 7[7]Taylor G W.The effects of two-dimensional charge sharing on the above threshold voltage characteristics of short channel IGFETs.IEEE Trans Electron Devices,1978,25(12):337
  • 8[8]Salcedo J A,Ortiz-Conde A,Sanchez E J G,et al.New approach for defining the threshold voltage of MOSFETs.IEEE Trans Electron Devices,2001,48(4):809
  • 9[9]Lai Keji,Zhang Li,Tian Lilin.Modeling and parameter extraction of VDMOSFET.Chinese Journal of Semiconductors,2002,23:251
  • 10[11]Pocha M D,Gonzalez A G,Dutton R W.Threshold voltage controllability in double-diffused-MOS transistors.IEEE Trans Electron Devices,1974,21(12):778

共引文献15

同被引文献56

引证文献10

二级引证文献24

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部