基于FPGA快速AES算法IP核的设计与实现

The Implementation of AES Algorithm IP Core in FPGA

用硬件实现数据加密过程比软件实现更具有优势,已成为信息安全的主流方向。数据传输速度则是加密系统的一个重要指标。文章基于FPGA采用流水线技术和优化设计,提出了一种更高效的AES算法IP核的设计方法。在使用较低时钟频率的情况下,获得了更大的数据吞吐量和更快的传输速度。

Hardware Implementation of data encryption has become the mainstream in information security field,because it has many advantages when compared with software implementation.Transmission speed is an important parameter of the encryption system.This paper presents an efficient design of AES algorithm＇s IP core in FPGA using pipelining technique and optimized methods.This implementation results in greater throughputs and less resource requirements.