mesh结构NoC的时钟网络研究

A Mixed-Architecture Clock Network of the Mesh NoC(Network on Chip)

分析了m esh结构N oC的3种时钟网络,针对同步时钟网络瞬时功耗大,非对称瀑布网络(w aterfall)和对称瀑布网络通信延迟大的弊端,提出并设计了一种混合结构的时钟网络。并以4×4混合结构时钟网络为例,计算得出该时钟网络的最大通信延迟为非对称瀑布网络的12.5%,局部单方向数据流的通信延迟约为对称瀑布网络的25%,芯片的瞬时功耗约为同步时钟网络的50%。

Purpose. We propose a novel mixed-architecture clock network in order to make its power dissipation less than that of a synchronized one and to make its communication delays much less than those of an asymmetrical waterfall one （non-synchronous） or a symmetrical waterfall one（non-synchronous）. In the full paper, we explain in detail our novel mixed-architecture clock network of the mesh NoC; here we just list the two topics of explanation. （1） mesh architecture of NoC and clock network ; subtopics are the analysis of communication delays of an asymmetrical waterfall clock network（subtopic 1.1） and analysis of communication delays of a symmetrical waterfall clock network（subtopic 1.2）; under subtopic 1.1, eqs. （1） through （4） in the full paper are derived; under subtopic 1.2, eq. （5） is derived;（2） the mixed-architecture clock network; the subtopics are the analysis and design of mixed-architecture clock network （subtopic 2.1） and the communication delay model of mixed-architecture clock network （subtopic 2, 2）; under subtopic 2. 2, eq. （6） is derived . For a 4 × 4 mesh NoC numerical example, its novel mixed- architecture clock network＇s longest communication delay is about 12.5 % of the asymmetrical waterfall＇s, its communication delay of the local one direction data-stream is about 25 % of the symmetrical waterfall＇s and its transient power dissipation is about 50% of the synchronized clock network＇s.