DDR SDRAM在高速数据采集系统中的应用与设计

Application and Design of DDR SDRAM to High Speed Data Acquisition System

本文针对高速数据采集系统中数据存储容量的瓶颈，提出了一种基于DDR SDRAM的采样存储架构。文中详细阐述了DDR存储控制状态机的设计原理、方法，以及在采集系统中存储控制的时序设计，并绐出了设计仿真及实验结果。

This paper presents a design of DDR SDRAM based data storage architecture, which is a solution to the limitation of the sampling storage capability in high speed data acquisition system. The emphasis of the paper is on DDR SDRAM controller that adopts Finite State Machine （FSM） described in three aspects： the principle, the scheme and the timing constraints. The paper also provides the simulation and results.