数字匹配滤波器的递归折叠实现

Recursive and Folded Implementation of Digital Matched Filter

针对数字匹配滤波器(DMF)的FPGA实现提出一种优化结构.利用16位移位寄存器(SRL16E)的存储潜力,设计递归延迟线(RDL);再利用RDL抽头个数倍减而抽头样本速率倍增的特点和时分复用技术,提出DMF的递归折叠结构.该结构以提高工作时钟频率为代价,增大延迟线的采样率以及相关运算单元的吞吐率,从而成倍降低DMF的资源消耗.当采用1/4递归折叠结构时,资源消耗仅为优化前的1/3.

An optimized structure of FPGA realization for digital matched filters（DMF） is presented. By fully applying the storage potential of 16 bit shift register LUT （SRL16E）, a recursive delay line （RDL） is proposed with the characters of multiplicative decrease of taps number and increase of taps＇ sample rate. Recursive folded DMF based on RDL and time-division multiplexing is also analyzed. By using the optimized structure, the sample rate of delay line and the throughput of correlation-calculation unit （CCU） are both increased, and the resource consumption of DMF is decreased greatly at the price of increasing clock frequency. The resource consumption of 1/4 recursive folded structure of DMF is only 1/3 of the consumption of unoptimized structure.