浮点加法器IP核的VHDL设计

Design of Floating-Point Adder IP Core Using VHDL

浮点数加法运算是浮点运算中使用频率最高的运算。结合VHDL和FPGA可编程技术,完成具有5级流水线结构、符合IEEE 754浮点数标准、可参数化为单/双精度的浮点数加法器IP核的VHDL设计。

The Floating-point addition is the highest frequent operator. Using the VHDL and programmable technology on PFGA, this paper discusses the design of floating-point adder IP core that implements in 5-stage pipeline architecture, be conformed to IEEE 754 standard and configured to single/double precision with variable parameter using VHDL.