基于FPGA的数控测试系统设计

Design of Numerical Control Testing System Based on FPGA

基于超高速集成电路硬件描述语言(VHDL)的数控测试系统,含控制信号、接收数据、数据处理及发送数据模块。根据不同控制信号,数据处理模块得到分频数据、主轴编码器输出个数和主轴编码器线数。由数据SPDL_SD产生主轴脉冲分频脉冲,再由分频脉冲DIV控制产生SPDL_NUM/4个正交的A、B脉冲,同时根据数据SPDL_XS产生Z脉冲。通过外部的输出电路,把产生的主轴A、B、Z脉冲发送到被测的数控系统。

The numerical control testing system which includes control signal module, RXD module, data processing module and TXD module is based on VHDL. The data processing module gained the dividing frequency data, the principal axis coder exportation piece and the principal coder line number based on different control signals. The module produced DIV pulse by the data of SPDL_SD; then produced quarter SPDL_NUM orthoclastic A, B pulse by DIV pulse; at the same time the module produced Z pulse by the data of SPDL_XS. Through the exportation electric circuit of the exterior, the principal axis A, B, Z pulse was sent out to the measured numerical control system.