堆叠(PoP)组装的挑战

Assembly challenges of Package-on-package (PoP)

提出了一种大批量堆叠(PoP)组装方法,这种方法利用了倒装芯片组装中已有的电子封装技术,讨论了多个挑战和考虑因素;演示了怎样使用自动贴装机和倒装芯片组装使用的选项、堆叠和组装这些模块。为适应底部CSP较大的球体尺寸及使用焊膏和助焊剂,必须进行某些改动,堆叠要求的精度要高于标准SMT贴装,某些现有的SMT贴装机可以进行改进,采用相应的改动精确地高速贴装堆叠的CSP,这种方法在成本上非常有竞争力。

This article proposes an approach to high volume Package-on-Package （POP） assembly that leverages the existing electronics packaging technologies for flip chip assembly. Several challenges and considerations are discussed. This article will demonstrate how to stack and assemble these modules by using automated placement machines and options used for flip chip assembly. Some modifications are re- quired to accommodate the larger ball size of the bottom CSP as well as the use of solder paste in addition to flux. Stacking requires more accuracy than standard SMT placement Some existing SMT assembly machines can be modified to accurately place stacked CSP＇s at high speeds with the appropriate modifications. This approach can be very cost competitive.