一种基于FPGA/CPLD的脉冲测距系统译码方案

A Decoding Scheme in Pulse Distance Measuring System Based on FPGA/CPLD

在数字化脉冲测距系统中,译码电路起着至关重要的作用。它可以提高系统的抗干扰性和测距准确性的能力。因此选择一套有效、简捷的译码电路是十分必要的。文中在研究了脉冲延迟译码的基础上,提出了一种更为简捷的译码方案,它在功能上可以完全替代前者,并且这种方案具有较强的灵活性、可扩展性,使设计者在设计时提高效率。

Decoding circuit is a vital part in pulse distance measuring system, because it can improve the anti-jamming ability and increases the veracity of distance measuring. Therefore, it is necessary to design an efficient and concise decoding circuit. Based on the investigation of delaying the first pulse for decoding, the author find a more concise decoding circuit. It can completely substitute the former method, furthermore, the method＇s agility and expansibility can enhance the designer＇s efficiency.