一种基于LFSR与MARCH C+算法的SRAM内建自测电路设计

A design of SRAM build-in self-test circuits based on LFSR and MARCH C+

提出了一种基于LFSR与MARCH C+算法的SRAM内建自测试新结构,基于此结构设计了2k×8嵌入式静态存储器(SRAM)的内建自测电路,给出了电路的仿真与综合结果。对比分析了这种新结构与传统结构的特性,指出这种新结构具有可复用性、面积较小、速度较快、故障覆盖率高等优点,是一种实用的、可推广应用的内建自测试结构。

This paper presents a new build-in self-test structure of SRAM based on LFSR and MARCHC ＋, which is designed for a 2K 〉（8 embedded SRAM. The simulation waveform and synthesis results are provided as well. The key point of this structure is the use of LFSR（linear feedback shift registers） as the address generator. Comparing with the traditional BIST structure of SRAM, the new one is reusable, compact, rapid and of high fault coverage, which is practical and prospective.