摘要
通过对传统串行CRC(循环冗余校验)电路中各移位寄存器状态的观察与分析,推导出并行算法的逻辑关系式,使用Verilog-hd l语言实现了并行算法并给出了仿真结果,仿真结果表明与串行算法相比并行算法提高了校验速率。
Through the observation of each shift register＇s state in the conventional serial CRC（ Cyclic Redundancy Check） circuit, Boolean expressions of parallel CRC algorithm are deduced. The realizing method based onVerilog - HDL and its simulation resuits are presented , and the simulation results show that parallel algorithm is more efficient than serial algorithm.
出处
《计算机与数字工程》
2006年第9期112-114,共3页
Computer & Digital Engineering
